LOGICLABUZ: A BROWSER-NATIVE CO-SIMULATION PLATFORM FOR THE VIRTUALIZATION OF MULTI-MCU ROBOTIC SYSTEMS
DOI:
https://doi.org/10.5281/zenodo.20706505Keywords:
embedded systems; microcontroller simulation; co-simulation; cycle-accurate emulation; circuit virtualization; educational tools; AVR.Abstract
Faithful virtualization of a microcontroller-based robotic system requires three capabilities that existing tools rarely
combine: cycle-accurate execution of the real instruction set, a continuous-domain electrical model of the surrounding circuit,
and a scheduler that couples the two at interactive speed. This paper presents Logiclabuz, a browser-native co-simulation
platform that provides all three. The simulator implements the full instruction set of three AVR variants, drives a library of
more than fifty electrically modeled components through a DC circuit solver with a fault layer, and infers multi-MCU UART,
SPI, and I²C links from the wire topology. Two design choices carry the performance: a unified data-space buffer that removes
per-region branching from the instruction hot path, and a two-tier scheduler that amortizes peripheral evaluation while preserving
cycle-accurate timer reads through linear interpolation. On a ten-workload benchmark, Logiclabuz runs 1.39 to 4.58
times faster than avr8js, the closest open browser comparator, reaching 59 to 171 million simulated cycles per second; the
scheduler alone accounts for an 11.7 to 43.6 times speedup over per-cycle evaluation. A conformance harness against simavr
1.7 and avr8js 0.21.0 establishes bit-for-bit agreement on the CPU instruction subset, and a 60-circuit benchmark yields a
macro F1 of 0.81 for the fault detector. The platform is deployed at https://logiclab.uz.
References
J.-M. Pollet, “Simavr: A lean, mean and hackable AVR simulator for linux & co.” https://github.com/buserror/simavr.
U. Wasserman, “avr8js: AVR 8-bit simulator written in TypeScript.” https://github.com/wokwi/avr8js.
S. Garcia, “SimulIDE: A real-time electronic circuit simulator.” https://www.simulide.com.
Autodesk, “TinkerCad circuits.” https://www.tinkercad.com/circuits.
Labcenter Electronics, “Proteus design suite — VSM.” https://www.labcenter.com.
I. Y. Abdullaeva and K. Khurana, “The impediments to the process of implementing robotics in the school education
system in Uzbekistan,” SAGE Open, vol. 14, no. 2, 2024, DOI: 10.1177/21582440241254595.
A. Ergashev, “Lazy-synchronization with interpolated state for discrete-continuous co-simulation of microcontrollerdriven
circuits.” 2026.
U. Wasserman, “Wokwi: Online IoT and microcontroller simulator.” https://wokwi.com.
L. W. Nagel, “SPICE: A computer program to simulate semiconductor circuits,” University of California, Berkeley,
Memorandum No. ERL-M520, 1975.
G. S. Wolffe, W. Yurcik, H. Osborne, and M. A. Holliday, “Teaching computer organization/architecture with limited
resources using simulators,” in Proceedings of the 33rd SIGCSE technical symposium on computer science education
(SIGCSE 2002), Cincinnati, KY, USA: ACM, 2002, pp. 176-180. DOI: 10.1145/563340.563408.
J. Lima, D. A. Gomes, J. E. Souto, and T. F. Vieira, “Use of Tinkercad platform for teaching electronics subject in post
secondary technical courses,” in Proceedings of the 9th international conference on technological ecosystems for
enhancing multiculturality (TEEM 2021), Barcelona, Spain: ACM, 2021, pp. 670-675. DOI: 10.1145/3486011.3486517.
J. Kholkhujaev, F. Khusnuddinov, and S. Kengesbayeva, “Review of industrial robot and robotic simulator market and
available education platforms for robotics learning in Uzbekistan,” Acta of Turin Polytechnic University in Tashkent, vol.
, no. 2, pp. 61-64, 2024, Available: https://acta.polito.uz/index.php/journal/article/view/287
P. Galkin, R. Umiarov, and O. Grigorieva, “Design embedded system testbench based on FPGA and microcontrollers
for TATU smart lab as education component of Industry 4.0,” in Proceedings of the 2019 IEEE 2nd ukraine conference
on electrical and computer engineering (UKRCON), 2019, pp. 628-633. DOI: 10.1109/UKRCON.2019.8879996.
R. O’Callahan, C. Jones, N. Froyd, K. Huey, A. Noll, and N. Partush, “Engineering record and replay for deployability,”
in Proceedings of the 2017 USENIX annual technical conference (USENIX ATC ’17), Santa Clara, CA, USA: USENIX
Association, 2017, pp. 377-389.
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